1. Field of the Invention
The present invention pertains to computer systems and computer system buses. More particularly, this invention relates to controlling data flow on a computer system bus which supports two- and three-agent transactions.
2. Background
Modern computer systems typically have multiple agents coupled together via a system bus. Typically, the agents are integrated circuit chips with multiple pins coupling each agent to the bus. These agents may include, for example, a processor(s), a memory device(s), a mass storage device(s), etc. In order for the computer system to operate properly, these agents should be able to effectively communicate with each other via the bus.
One aspect of this communication is the transfer of data from one agent to another. The transfer of data on the bus is referred to as the data flow on the bus. In many computer systems, an agent which can be the target of a data transfer has a storage space, such as a data buffer, into which the transferred data is placed. However, agents typically have a limited amount of storage space for data. Therefore, situations can arise where the targeted agent for a data transfer does not have sufficient storage space to store the data. Additionally, it is often the case that only the targeted agent knows whether it has sufficient storage space to store the data. Thus, it would be beneficial to provide a mechanism that allows the agent which is targeted by a request to control the flow of data on the bus for that request.
Additionally, one type of bus which can be used in a computer system is referred to as a latched bus. In a latched bus system, data is latched into a storage space from the bus in one clock cycle and control signals based on that data can be placed on the bus in any of the subsequent clock cycles. In contrast, in a non-latched bus system, data is received from the bus in one clock cycle and control signals based on that data can be placed on the bus in that same clock cycle. Due to the nature of the latched bus, some solutions for controlling data flow on the bus which work on a non-latched bus are too inefficient to work on a latched bus. For example, on a non-latched bus, data can be placed on the bus by a source agent which can wait until it receives a ready signal from the targeted agent, at which point the source agent provides, in the same clock cycle as it receives the ready signal, the next data. However, this concept of waiting for, receiving, and processing the ready signal for each data transfer takes too much time on a latched bus because the ready signal would be received in one clock cycle, processed in the next clock cycle, and then the next data would be placed on the bus. Therefore, it would be beneficial to provide a mechanism that allows the targeted agent to more efficiently control the flow of data on a latched bus.
Furthermore, some computer systems include one or more cache memories, each of which is faster and smaller than the main system memory. The cache memory typically allows data which has been recently accessed by an agent, or which is predicted to be accessed soon by an agent, to be available in a faster memory, thereby reducing the time required to obtain the data and increasing overall system performance. Different agents, such as different processors, on a bus will often have their own cache memory. These agents are then able to modify the data stored in their cache memory without making the same modifications to the main memory until a later time. However, situations can arise where data which is requested by a first agent is stored in a cache memory of a second agent, and the requested data in the second agent""s cache memory has been modified. Therefore, the data to be returned to the first agent should come from the cache memory of the second agent, not from the main memory because the data in the cache memory is a more recent version. One solution to this problem is to transfer the requested data from the second agent to the first agent and have the memory controller for the main memory also take the data off the bus. A transaction such as this which uses the first and second agents, as well as the memory controller, is referred to as a three-agent transaction. However, this solution presumes that the memory controller has sufficient storage space to take the data off the bus, which is not always the case. Thus, it would be beneficial to provide a mechanism which allows the memory controller to maintain data flow control on the bus for a three-agent transaction.
As will be described in more detail below, the present invention provides a data flow control mechanism for a bus supporting two- and three-agent transactions to achieve these and other desired results which will be apparent to those skilled in the art from the description that follows.
A data flow control mechanism for a bus supporting two- and three-agent transactions is described herein. An apparatus in accordance with the data flow control mechanism of the present invention includes a control logic to place an indication of a request onto a computer system bus. The apparatus then waits to place data corresponding to the request onto the bus until it has received an indication from an agent coupled to the bus that the agent is ready to receive the data.
In one embodiment of the present invention, the data flow control mechanism supports both two- and three-agent transactions. In a two-agent transaction in accordance with this embodiment, data is transferred from a source agent to a target agent, with the target agent maintaining control of the data flow. In a three-agent transaction in accordance with this embodiment, data is transferred from a snooping agent to either the source agent or the target agent, as well as possibly from the source agent to the target agent. In the three-agent transaction, the target agent controls the data flow of transfers to the target agent, regardless of whether they originated with the source agent or the snooping agent.